The production of semiconductor devices at decreasing geometries and at lower costs has long been recognized as one of the key contributing factors to the widespread benefits of the digital age. The cost of a semiconductor device is set largely by the size of the substrate, the cost of materials that are consumed as the substrate is processed, and by the amount of capital overhead that is assignable to each part. The first two contributors to cost can be reduced by decreasing the size of the device, and by utilizing readily available materials. Capital overhead costs can be decreased by using readily available manufacturing equipment, and through the development of processing techniques that eliminate the need for more exotic equipment and reduce the time it takes to build each device. These processing techniques are sometimes associated with distinctive manufacturing features that provide evidence of how the device was made.
A self-aligned gate is a manufacturing feature that is indicative of a particular processing technique that can be described with reference to FIG. 1. Semiconductor wafer 100 comprises a substrate 101 covered by gate 102. As illustrated, gate 102 includes a photomask 103, a gate electrode 104, and a gate insulator 105. At this point in the process, photomask 103 has been used to create the gate stack. In other words, gate electrode 104 and gate insulator 105 previously had additional portions such that they extended lateral across the surface of substrate 101. Photomask 103 was then used to shield the gate stack while those additional portions were removed. Once gate 102 has been formed, photomask 103 can be put to use in another processing step. As illustrated in FIG. 1, gate 102 can serve as a mask to shield channel 107 while wafer 100 is exposed to a diffusion of dopants 108. As a result, photomask 103 can be used to not only form the gate stack, but also to create the source and drain regions of the transistor 109. Therefore, a different mask is not required for the creation of gate stack 102 and source and drain regions 109.
In addition to reducing the number of processing steps required, a self-aligned gate process produces an additional benefit in that the resulting device has superior characteristics when compared to devices formed according to certain alternative processing methodologies. The performance of a transistor is directly impacted by the interdependence of the gate, channel, source, and drain regions of the transistor. In particular, it is important to tightly control the location of the source-channel and drain-channel junctions relative to the gate of the transistor. As the same mask is used to form both the gate stack and the source and drain regions in a self-aligned gate process, errors resulting from the misalignment of two different masks are eliminated. The self-aligned gate process therefore provides for both a more cost effective and functionally superior device.